End-host stacks for datacenter class applications - 2026_CDR_DEIB_11

The research activity will investigate novel system architectures for accelerating the network stack of data-center-class applications. The work will focus on the co-design of operating-system mechanisms, networking software, and programmable hardware accelerators to improve the performance and efficiency of high-throughput, data-intensive workloads. A key objective will be to identify network-processing functions that can benefit from hardware acceleration while retaining flexibility and programmability. The research will explore extensions to operating systems and networking stacks that enable applications to exploit hardware acceleration capabilities available in novel NIC architectures. Particular attention will be devoted to hardware-software interaction, including mechanisms for data movement, communication, synchronization, and dynamic allocation of processing between the host and the NIC.